1. Field of the Invention
The present invention relates to a data transfer control method, a data transfer control system, and an information recording medium in an information processing apparatus having a computer arrangement in which DMA controllers are connected to a common bus and data transfer is performed.
2. Description of the Related Art
Generally speaking, in an information processing apparatus, for a purpose of transmission and reception of data with a peripheral device, a DMA controller (hereinafter, simply referred to as a `DMAC`) is connected to a system bus or an I/O bus, and, by using the DMAC, DMA (Direct Memory Access) is performed, that is, a memory is directly accessed.
In many cases, data transfer performed with a peripheral device is performed in an asynchronous method, and data transfer is performed with handshaking. In such a case, a capacity of a bus used for data transfer is not previously known clearly.
Further, when data transfer is performed synchronously with a peripheral device or a network, a capacity of a bus used when the synchronous data transfer is performed, a maximum capacity of the bus used when data transfer is performed, and, also, a capacity of the bus used when a transaction is performed by a CPU are considered. Thus, a specification of the bus is determined, and, the bus is designed, or the bus is obtained, as a result of selection. Thereby, it is guaranteed that the entire transaction is performed without stagnation.
However, thereby, the specification of the bus is excessive except for a rare case where congestion of the bus occurs.
Further, in an expansion I/O, it is not determined at a timing of designing a system as to which expansion board is to be inserted and what amount of data transfer is required. Thereby, unexpected congestion occurs in a bus when the system is actually used, and data transfer may not be performed without stagnation.
In particular, in data transfer control in an information processing apparatus in the related art, a capacity of a bus used when a DMAC, a CPU, and so forth use the bus, and a capacity of the bus used when data transfer is performed by a peripheral device are not considered. As a result, a new DMA is started when new data transfer is requested from an application program or the like even in a condition where the bus is already saturated. When such a situation occurs, loss of data occurs in an interface which performs synchronous data transfer using a certain capacity of the bus. Thus, a serious situation may occur in the system. Such a problem may occur not only in an interface using the newly started DMA but also in every interface which performs synchronous data transfer.
For example, when data transfer in a new interface performed by an application program or the like is required under a condition where data transfer in an interface, which needs data transfer of a fixed data transfer rate, such as a video interface, a network interface or the like, has already been performed by using a common bus, a new DMA is started even in a case where there is no sufficient free capacity of the bus. As a result, the data transfer is not guaranteed. Such a problem may occur in particular in a case where successive data transfer such as that of an operation for copying a large amount of data or data transfer by a periodically performed program is required.
Further, for example, in a case of using an IEEE 1394, in which data of frequencies of 100 MHz, 200 MHz and 400 MHz are mixed in one interface, a data transfer rate of data reception is not known until data from the interface is actually received, and, thus, a capacity of a bus needed for DMA used for storing the data in a memory cannot be previously known. As a result, the data may not be completely stored in the memory.
In an interface for asynchronous data transfer, because data transmission and reception is performed with handshaking, a data transfer rate depends on a particular device with which communication is performed, and, thus, a capacity of bus needed for DMA used for storing data in a memory cannot be previously known. As a result, data may not be completely stored in the memory for a particular device with which communication is performed.